Enum scir::validation::Cause
source · pub enum Cause {
DuplicateCellNames {
id1: CellId,
id2: CellId,
name: ArcStr,
},
DuplicateInstanceNames {
inst_name: ArcStr,
cell_id: CellId,
cell_name: ArcStr,
},
DuplicateSignalNames {
id1: SignalId,
id2: SignalId,
name: ArcStr,
cell_id: CellId,
cell_name: ArcStr,
},
ShortedPorts {
signal: SignalId,
name: ArcStr,
cell_id: CellId,
cell_name: ArcStr,
},
MissingSignal {
id: SignalId,
cell_id: CellId,
cell_name: ArcStr,
},
MissingChild {
child_id: ChildId,
parent_cell_id: CellId,
parent_cell_name: ArcStr,
instance_name: ArcStr,
},
UnconnectedPort {
child_cell_id: CellId,
child_cell_name: ArcStr,
port: ArcStr,
parent_cell_id: CellId,
parent_cell_name: ArcStr,
instance_name: ArcStr,
},
ExtraPort {
child_cell_id: CellId,
child_cell_name: ArcStr,
port: ArcStr,
parent_cell_id: CellId,
parent_cell_name: ArcStr,
instance_name: ArcStr,
},
IndexOutOfBounds {
idx: usize,
width: usize,
cell_id: CellId,
cell_name: ArcStr,
},
MissingIndex {
signal_name: ArcStr,
cell_id: CellId,
cell_name: ArcStr,
},
IndexedWire {
signal_name: ArcStr,
cell_id: CellId,
cell_name: ArcStr,
},
PortWidthMismatch {
expected_width: usize,
actual_width: usize,
instance_name: ArcStr,
port: ArcStr,
parent_cell_id: CellId,
parent_cell_name: ArcStr,
child_cell_id: CellId,
child_cell_name: ArcStr,
},
}
Expand description
The cause of a SCIR error or warning.
Variants§
DuplicateCellNames
Fields
name: ArcStr
The conflicting name.
Two or more cells have the same name.
DuplicateInstanceNames
Two instances in the same cell have the same name.
DuplicateSignalNames
Two signals in a cell have the same name.
ShortedPorts
A signal is listed as a port more than once.
MissingSignal
Fields
cell_name: ArcStr
The name of the cell containing the missing signal.
A signal identifier is used but not declared.
MissingChild
Fields
parent_cell_name: ArcStr
The name of the parent cell.
instance_name: ArcStr
The name of the offending instance.
An instance in a parent cell references a child not present in the library.
UnconnectedPort
Fields
child_cell_name: ArcStr
The name of the child cell.
port: ArcStr
The name of the unconnected port.
parent_cell_name: ArcStr
The name of the cell containing the offending instance.
instance_name: ArcStr
The name of the instance in the parent cell.
An instance does not specify a connection to a port of its child cell.
ExtraPort
Fields
child_cell_name: ArcStr
The name of the child cell.
port: ArcStr
The name of the port the instance is trying to connect.
parent_cell_name: ArcStr
The name of the cell containing the offending instance.
instance_name: ArcStr
The name of the offending instance in the parent cell.
An instance specifies a connection to a port that does not exist in the child cell.
IndexOutOfBounds
Fields
cell_name: ArcStr
The name of the offending cell.
A bus index is out of bounds given the width of the bus.
MissingIndex
Used a bus without indexing into it.
IndexedWire
Attempted to index a single wire.
PortWidthMismatch
Fields
instance_name: ArcStr
The name of the offending instance.
port: ArcStr
The name of the port with the invalid connection.
parent_cell_name: ArcStr
The name of the parent cell.
child_cell_name: ArcStr
The name of the child cell.
An instance specified a connection of incorrect width.
Trait Implementations§
source§impl<'de> Deserialize<'de> for Cause
impl<'de> Deserialize<'de> for Cause
source§fn deserialize<__D>(__deserializer: __D) -> Result<Self, __D::Error>where
__D: Deserializer<'de>,
fn deserialize<__D>(__deserializer: __D) -> Result<Self, __D::Error>where
__D: Deserializer<'de>,
source§impl PartialEq for Cause
impl PartialEq for Cause
impl Eq for Cause
impl StructuralPartialEq for Cause
Auto Trait Implementations§
impl RefUnwindSafe for Cause
impl Send for Cause
impl Sync for Cause
impl Unpin for Cause
impl UnwindSafe for Cause
Blanket Implementations§
source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
§impl<Q, K> Equivalent<K> for Q
impl<Q, K> Equivalent<K> for Q
§fn equivalent(&self, key: &K) -> bool
fn equivalent(&self, key: &K) -> bool
§impl<Q, K> Equivalent<K> for Q
impl<Q, K> Equivalent<K> for Q
§fn equivalent(&self, key: &K) -> bool
fn equivalent(&self, key: &K) -> bool
key
and return true
if they are equal.