Expand description
Schematic cell intermediate representation (SCIR).
An intermediate-level representation of schematic cells and instances.
Unlike higher-level Substrate APIs, the structures in this crate use strings, rather than generics, to specify ports and connections.
This format is designed to be easy to generate from high-level APIs and easy to parse from lower-level formats, such as SPICE or structural Verilog.
SCIR supports single-bit wires and 1-dimensional buses. Higher-dimensional buses should be flattened to 1-dimensional buses or single bits when converting to SCIR.
Single-bit wires are not exactly the same as single-bit buses:
A single bit wire named x will typically be exported to netlists as x,
unless the name contains reserved characters or is a keyword in the target
netlist format.
On the other hand, a bus named x with width 1
will typically be exported as x[0].
Furthermore, whenever a 1-bit bus is used, a zero index must be specified.
However, single bit wires require that no index is specified.
Zero-width buses are not supported.
Modules§
- drivers
- SCIR driver validation.
- merge
- Merge SCIR libraries.
- netlist
- Netlist export.
- schema
- Traits and definitions associated with schemas, or data formats used for storing SCIR libraries.
- validation
- SCIR validation utilities.
Structs§
- Annotated
Instance Path - A path to an instance in a SCIR library with annotated metadata.
- Annotated
Instance Path Element - An element of an
AnnotatedInstancePath. - Cell
- A cell.
- CellId
- An opaque cell identifier.
- Concat
- A concatenation of multiple slices.
- Instance
- An instance of a child cell placed inside a parent cell.
- Instance
Id - An opaque instance identifier.
- Instance
Path - A path to an instance in a SCIR library.
- Issues
- Issues encountered when validating a SCIR library.
- Library
- A SCIR library that is guaranteed to be valid (with the exception of primitives, which are opaque to SCIR).
- Library
Builder - A library of SCIR cells with schema
S. - Named
Path - A path of strings to an instance or signal in a SCIR library.
- Named
Slice - A single bit wire or a portion of a bus signal addressed by name.
- Named
Slice One - A single bit wire or a single bit of a bus signal addressed by name.
- Netlist
Cell Conversion - Metadata associated with the conversion from a SCIR cell to a netlisted subcircuit.
- Netlist
LibConversion - Metadata associated with the conversion from a SCIR library to a netlist.
- Port
- A signal exposed by a cell.
- Primitive
Id - An opaque primitive identifier.
- Signal
Id - An opaque signal identifier.
- Signal
Info - Information about a signal in a cell.
- Slice
- A single bit wire or a portion of a bus signal.
- Slice
One - A single bit wire or a single bit of a bus signal.
- Slice
OnePath - A path to a nested
SliceOne. - Slice
Path - A path to a nested
Slice. - Slice
Range - A range of bus indices.
Enums§
- ChildId
- The ID of an instance’s child.
- Direction
- Port directions.
- Instance
Path Cell - The cell within an
InstancePath. - Instance
Path Cell Ref - The cell within an
InstancePath. - Instance
Path Element - An element of an
InstancePath. - Instance
Path Element Ref - An element of an
InstancePath. - Param
Value - A value of a parameter.
- Signal
Path Tail - The end of a signal path.
Traits§
- Index
Owned - Index into an object.