Module substrate::io

Traits and types for defining interfaces and signals in Substrate.

Modules

• layout
  Traits and types for schematic IOs.
• schematic
  Traits and types for schematic IOs.

Structs

• Array
  An array containing some number of elements of type T.
• ArrayData
  An instantiated array containing a fixed number of elements of type T.
• DiffPair
  A pair of differential signals.
• DiffPairLayout
  A pair of differential signals.
• DiffPairLayoutBuilder
  A pair of differential signals.
• DiffPairNestedSchematicView
  A pair of differential signals.
• DiffPairNestedTerminalView
  A pair of differential signals.
• DiffPairSchematic
  A pair of differential signals.
• DiffPairTerminalView
  A pair of differential signals.
• DiffPairTransformedLayout
  A pair of differential signals.
• Flipped
  Flip the direction of all ports in T
• InOut
  An inout port of hardware type T.
• Input
  An input port of hardware type T.
• MosIo
  The interface to a standard 4-terminal MOSFET.
• MosIoLayout
  The interface to a standard 4-terminal MOSFET.
• MosIoLayoutBuilder
  The interface to a standard 4-terminal MOSFET.
• MosIoNestedSchematicView
  The interface to a standard 4-terminal MOSFET.
• MosIoNestedTerminalView
  The interface to a standard 4-terminal MOSFET.
• MosIoSchematic
  The interface to a standard 4-terminal MOSFET.
• MosIoTerminalView
  The interface to a standard 4-terminal MOSFET.
• MosIoTransformedLayout
  The interface to a standard 4-terminal MOSFET.
• NameBuf
  An owned node name, consisting of an ordered list of NameFragments.
• NameTree
  A tree for hierarchical node naming.
• Output
  An output port of hardware type T.
• PowerIo
  The interface for VDD and VSS rails.
• PowerIoLayout
  The interface for VDD and VSS rails.
• PowerIoLayoutBuilder
  The interface for VDD and VSS rails.
• PowerIoNestedSchematicView
  The interface for VDD and VSS rails.
• PowerIoNestedTerminalView
  The interface for VDD and VSS rails.
• PowerIoSchematic
  The interface for VDD and VSS rails.
• PowerIoTerminalView
  The interface for VDD and VSS rails.
• PowerIoTransformedLayout
  The interface for VDD and VSS rails.
• Signal
  A type representing a single hardware wire.
• TestbenchIo
  The interface to which simulation testbenches should conform.
• TestbenchIoLayout
  The interface to which simulation testbenches should conform.
• TestbenchIoLayoutBuilder
  The interface to which simulation testbenches should conform.
• TestbenchIoNestedSchematicView
  The interface to which simulation testbenches should conform.
• TestbenchIoNestedTerminalView
  The interface to which simulation testbenches should conform.
• TestbenchIoSchematic
  The interface to which simulation testbenches should conform.
• TestbenchIoTerminalView
  The interface to which simulation testbenches should conform.
• TestbenchIoTransformedLayout
  The interface to which simulation testbenches should conform.
• TwoTerminalIo
  The interface for 2-terminal blocks.
• TwoTerminalIoLayout
  The interface for 2-terminal blocks.
• TwoTerminalIoLayoutBuilder
  The interface for 2-terminal blocks.
• TwoTerminalIoNestedSchematicView
  The interface for 2-terminal blocks.
• TwoTerminalIoNestedTerminalView
  The interface for 2-terminal blocks.
• TwoTerminalIoSchematic
  The interface for 2-terminal blocks.
• TwoTerminalIoTerminalView
  The interface for 2-terminal blocks.
• TwoTerminalIoTransformedLayout
  The interface for 2-terminal blocks.

Enums

• Direction
  Port directions.
• NameFragment
  A portion of a node name.

Traits

• Directed
  Indicates that a hardware type specifies signal directions for all of its fields.
• FlatLen
  The length of the flattened list.
• Flatten
  Flatten a structure into a list.
• HasNameTree
  An object with named flattened components.
• Io
  A trait implemented by block input/output interfaces.
• StructData
  A schematic hardware data struct.

Derive Macros

• Io
  Derives Io for a struct.