Crate scir

source ·
Expand description

Schematic cell intermediate representation (SCIR).

An intermediate-level representation of schematic cells and instances.

Unlike higher-level Substrate APIs, the structures in this crate use strings, rather than generics, to specify ports and connections.

This format is designed to be easy to generate from high-level APIs and easy to parse from lower-level formats, such as SPICE or structural Verilog.

SCIR supports single-bit wires and 1-dimensional buses. Higher-dimensional buses should be flattened to 1-dimensional buses or single bits when converting to SCIR.

Single-bit wires are not exactly the same as single-bit buses: A single bit wire named x will typically be exported to netlists as x, unless the name contains reserved characters or is a keyword in the target netlist format. On the other hand, a bus named x with width 1 will typically be exported as x[0]. Furthermore, whenever a 1-bit bus is used, a zero index must be specified. However, single bit wires require that no index is specified.

Zero-width buses are not supported.

Modules§

  • SCIR driver validation.
  • Merge SCIR libraries.
  • Traits and definitions associated with schemas, or data formats used for storing SCIR libraries.
  • SCIR validation utilities.

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